In general, it may be desirable to identify errors in semiconductor design while the semiconductor is in the design phase. As production moves from design to tooling and fabrication, the cost to fix design errors increases greatly. This great increase in cost may be attributable to specialized fabrication hardware that may have to be modified to repair a design error. A very small change in design can have cascading effects to other areas of the semiconductor. If these changes are made in while the semiconductor is in the design phase, software design tools can simply modify the architecture appropriately with little ramifications. If, however, a design error is found after production has transitioned to tooling and fabrication, a design change with cascading effects could necessitate the retooling of the entire line at considerable cost.
As design errors are much less costly to remedy while the semiconductor is in the design phase, much effort has been expended into methods of ensuring proper semiconductor designs in this stage. The process of ensuring proper design is referred to as verification. Design verification is generally focused into two areas: simulation and formal verification. Simulation involves testing the design against a sample set of inputs and checking the outputs against their expected values. Formal verification involves testing the universe of possible inputs against their expected outputs.